Integrated circuits (or chips) are tested before shipping to the market as well as in the field, e.g. when the integrated circuit is provided in a product in the hands of a consumer. More specifically, different modules within the integrated circuits are tested. Field testing occurs at designated times, for example, when a microprocessor boots up. Before running an application, the microprocessor has to check the modules to make sure that everything is working properly. When microprocessors fail debugging may be used to understand from where the failure originated.
These tests include functional testing and testing for timing defects, or delay fault testing. In functional testing, input signals are provided to the input of the module and an output of the module is checked to determine whether the correct output signals are generated in response to the particular input. All possible input signals to the module are provided and the response is checked for each individual input signal. Functional testing is applied to all modules. In addition, certain modules in which timing problems may play a greater role undergo further testing to determine if timing defects are present. For example, the Arithmetic Logic Unit (ALU) of a microprocessor undergoes both functional testing and testing for timing defects.
Some chips are relatively simple and have few modules. Input signals for these chips may be supplied directly from off chip to the modules via the pins on the chips. In an integrated circuit with many different modules, for example a microprocessor however, there are a large number of modules whose inputs are not available directly off chip. These modules instead may be driven by some other logic block. For efficiency, it is better to test individual modules separately.
A shift register is used in order to provide flexibility in controlling the input state supplied to individual modules while using the minimal number of pins in the chip. An embodiment of the known circuit 100 containing a shift register is shown in FIG. 1. The circuit 100 has an input block 110, a holding block 120 and a combinational logic block 130. The input block 110 is connected to the combinational logic block 130 through the holding block 120. Another shift register (not shown) is present at the output side of the combination logic block 130.
During testing times, the input block 110 has a plurality of flip-flops 112 (also called latches) cascaded such that the output Q of one of the latches 112 is essentially connected to the input D of the adjacent latch 112. Under normal (non-testing) operation conditions, the latches are configured so that they are independent of each other, rather than being serially connected. A clock signal CLK supplied to the input block 110 is applied to each latch 112. The input block 110 also includes a multiplexer 114 for each latch 112. A timing control signal TC supplied to the input block 110 is applied to each multiplexer 114 to activate the multiplexer 114. Signals from the combinational logic block 130 are supplied to one input of the multiplexer 114. A Scan In signal is supplied to another input of the multiplexer 114 associated with the first latch 112 in the shift register. The output of the multiplexer 114 is connected to the input of the associated latch 112. The output Q of each latch 112 subsequent to the first latch is connected to the input of multiplexer 114 associated with the next latch 112. The signal from the output Q of the last latch 112 is taken as a scan out signal from the input block 110.
The latches 112 hold the signals (or state) applied to the input until a new state is applied and the latches 112 are again triggered to pass the state to the output. Because chip packages usually do not provide a large number of pins, the number of pins used for testing is minimized. Accordingly, the latches 112 are loaded with a desired pattern serially from one pin of the overall chip. Similarly, it takes the same amount of time to load the response data from the shift register of the combinational logic block 130. After loading a desired state, the response of the combinational logic block is then captured and analyzed to determine if it is correct. A relatively large combinational logic block 130 may have several thousand inputs. Thus, it may take several thousand clock cycles in which intermediate vectors are loaded to completely load a particular sequence (also called vector) into the latches 112 and test the output of the combinational logic block 130. So before reaching the desired state, the latches 112 have to go through thousands of unwanted states to reach the final, desired state. If the input block 110 and combinational logic block 130 were connected directly, the logic elements such as AND, OR, and inverter gates inside the combinational logic block 130 would dissipate power as the intermediate vectors were loaded due to internal switching in the logic elements. The switching is charging and discharging of capacitance internal to the logic elements.
Energy dissipation during testing increases the temperature of the chip in which the combinational logic block is disposed, which in turn detrimentally affects the reliability of the chip. Because the test vectors loaded into the input block are totally random, switching activity in the combinational logic block is at a maximum. On the other hand, the patterns applied to many combinational logic blocks tend to be correlated, reducing the total amount of switching in contrast to the exhaustive and totally random patterns applied during testing. Thus, the temperature obtained during testing may be larger than that obtained under normal operating conditions. Power dissipation due to testing also markedly decreases the battery lifetime of portable applications such as laptops or cell phones.
If the intermediate vectors are prevented from propagating through the combinational logic block, then the combinational logic block does not experience redundant switching before reaching final state. Accordingly, as shown in FIG. 1, a holding block 120 containing holding logic 122 is inserted between the input block 110 and the combinational logic block 130. The outputs of the latches 112 are connected to the holding logic 122 in the holding block 120. The holding block 120 isolates the combinational logic block 130 from the input block 110 between when one final vector and the next final vector is loaded into the input block 110. The holding block 120 passes the final vector for one clock cycle. Either the timing control signal TC or a separate hold signal HOLD can be supplied to the holding block 120 to permit the final vector to pass therethrough.
However, even if the functionality of the combinational logic block is correct, the combinational logic block may be slower than a target speed due to processing variations during fabrication, limitation of timing models and static timing analysis tools, or physical defects for example. Thus, although the combinational logic block works properly at the relatively low speed used during the functional testing, it does not provide proper outputs when operating at the target speed. Accordingly, for modules operating at the higher target speed, usually the frequency of the system, a timing test is used to determine whether there is any delay failure in the response when applying one particular vector and then next applying another particular vector at the target speed. The arrangement of FIG. 1 is used to hold the first vector while the second vector is loading. After the second vector is loaded, it is applied to the combinational logic block so that the response to the change between the first and second vectors can be obtained.
However, there is a significant amount of area, power, and delay overhead involved in inserting the holding block in the arrangement of FIG. 1. The holding block contains thousands of extra logic gates. These logic gates use a relatively large amount of extra die area on the substrate on which the integrated circuit is fabricated. Increasing the area concomitantly decreases the number of integrated circuits that are able to be fabricated on a wafer. The holding block also remains in the circuit during normal operation when the combinational logic block is not being tested. Switching from the flip-flops in the input block propagates through the holding block to reach the combinational logic block. Thus, the holding block also experiences switching during normal operation and therefore causes some power dissipation. As the circuit goes through testing once in a while but remains in the normal mode for a much larger proportion of time, decreasing power by a little in the normal mode is saves more power than using a little more power in the test mode. Finally, the holding block causes a delay in propagation of the signals from the input block to the combinational logic block.